How do UCIe and BoW interconnects support generative AI on chiplets?

By Jeff Shepard, Microcontroller Tips (February 28, 2024)

The bunch-of-wires (BoW) and Universal Chiplet Interconnect Express (UCIe) standards provide designers with tradeoffs in terms of throughput, interconnect density, delay, and bump pitch. This FAQ compares the performance of BoW and UCIe and looks at how optical interconnects may provide a path to even higher performance interconnects in chiplets.

To realize optimal performance for generative artificial intelligence (AI), machine learning (ML), and other high-performance computing (HPC) applications, designers are turning to chipsets that can combine AI accelerators, GPUs, CPU, memory, and networking in a single package. Interconnecting heterogeneous devices in a chiplet can be especially challenging.

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