Alphawave Semi’s quest for open chiplet ecosystem

By Majeed Ahmad, EDN (June 17, 2024) 

The open chiplet ecosystem is steadily taking shape, one design demonstration at a time. Take, for instance, Alphawave Semi, which has announced the tape-out of what it claims to be the industry’s first off-the-shelf multi-protocol I/O connectivity chiplet on TSMC’s 7-nm process node.

This multi-standard I/O chiplet employs an IP portfolio complaint with Ethernet, PCIe, CXL, and Universal Chiplet Interconnect Express (UCIe) Revision 1.1 standards. It delivers a total bandwidth of up to 1.6 Tbps with up to 16 lanes of multi-standard PHY supporting silicon-proven PCIe 6.0, CXL 3.x, and 800G Ethernet IPs.

A couple of months ago, Alphawave Semi announced the development of a chiplet connectivity platform on TSMC’s 3-nm process node. It’s a UCIe subsystem comprising PHY and controller which can deliver 24 Gbps data rates. The 24-Gbps UCIe subsystem is compliant with the UCIe Revision 1.1 specification and includes a highly configurable die-to-die controller that supports streaming, PCIe/CXLTM, AXI-4, AXI-S, CXS, and CHI protocols.

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