GlobalFoundries, MIPS, and the Chiplet Race for AI Datacenters
Key Takeaways
- GlobalFoundries' acquisition of MIPS in 2025 positions it strategically in the AI, HPC, and datacenter sectors, securing CPU IP essential for modular compute.
- The shift to chiplet architectures in datacenters is driven by the limitations of monolithic scaling, with major companies like AMD, Intel, and Nvidia already adopting chiplet designs.
- Advanced packaging has become a critical bottleneck in AI chip supply, with GF needing to build in-house capabilities or establish deeper partnerships with OSATs to compete effectively.
GlobalFoundries’ (GF) acquisition of MIPS in 2025 wasn’t a nostalgic move to revive a legacy CPU brand. It was a calculated step into one of the most lucrative frontiers in semiconductors: AI, high-performance computing (HPC), and datacenters. As Nvidia, AMD, Intel, and hyperscalers embrace chiplet architectures, GF is betting that owning CPU IP will secure it a central role in the modular compute era.
Chiplets Reshape the Datacenter
The shift to chiplets in datacenters is now undeniable. AI training and inference workloads have pushed beyond the limits of monolithic scaling. Traditional GPUs and accelerators face reticle-size ceilings, yield problems, and soaring power and cooling demands. Chiplets solve these constraints by breaking compute into smaller dies—CPUs, GPUs, accelerators, memory, and I/O—then stitching them together with advanced interconnects.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Blogs
- Samsung Foundry Partners with Arm, ADTechnology and Rebellions to Develop an Innovative AI CPU Chiplet Platform Ideal for Modern AI Datacenters
- Intel® Shows OCI Optical I/O Chiplet Co-packaged with CPU at OFC2024, Targeting Explosive AI Scaling
- AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs
- Alphawave Semi Tapes Out Industry-First, Multi-Protocol I/O Connectivity Chiplet for HPC and AI Infrastructure
Latest Blogs
- Thermal Advances Driving Next-Gen AI Chip Design
- Designing the Future: How 3DIC Compiler Is Powering Breakthroughs Across the MultiDie Design Landscape
- Building out the Photonic Stack
- 2026 Predictions: System-Level Design, AI-Native Workflows, and the Rise of Multi-Die Compute Fabrics
- Accelerating Chiplet Integration in Heterogeneous IC Package Designs