Chiplet Technical Papers Archive - Page 3 of 10

MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging

By Jinwei Tang, University of Minnesota

August 29, 2025

ATSim: A Fast and Accurate Simulation Framework for 2.5D/3D Chiplet Thermal Design Optimization

By Qipan Wang, Peking University

August 29, 2025

Chiplet-Based Architectures: Redefining the Future of System-on-Chip (SoC) Design

By Hameed Ul Hassan Mohammed, ProteanTecs

August 22, 2025

AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems

By Ishraq Tashdid, University of Central Florida

August 20, 2025

THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures

By Alish Kanani, University of Wisconsin–Madison

August 19, 2025

LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural Exploration

By Ismael Youssef, Georgia Institute of Technology

August 18, 2025

Corsair: An In-memory Computing Chiplet Architecture for Inference-time Compute Acceleration

By Satyam Srivastava, d-Matrix Corporation

August 11, 2025

Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-based Systems-in-Package using Nanosheet Technology

By Yukai Chen, IMEC

August 6, 2025

Chiplets Are The New Baseline for AI Inference Chips

By Sid Sheth, d-Matrix Corp

August 5, 2025

Hybrid Bonding With Polymeric Interlayer Dielectric Layers Patterned by Nanoimprint Lithography

By Sungwoo Jeon, Seoul National University of Science and Technology

August 4, 2025

Advanced Optical Integration Processes for Photonic-Integrated Circuit Packaging

By Keuntae Baek, Hanyang University

August 4, 2025

Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond

By Shenggao Li, TSMC

August 2, 2025

A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration

By Wei-Hsing Huang, Georgia Institute of Technology

July 31, 2025

ChipletPart: Scalable Cost-Aware Partitioning for 2.5D Systems

By Alexander Graening, University of California

July 29, 2025

Chiplet design basics for engineers

By Andy Nightingale, Arteris

July 28, 2025

Electrothermal co-optimization of 2.5D power distribution network with TTSV cooling

By Yang Wang, Xidian University, China

July 18, 2025

Thermal Issues Related to Hybrid Bonding of 3D-Stacked High Bandwidth Memory: A Comprehensive Review

By Seung-Hoon Lee, Chungbuk National University

July 16, 2025

Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks

By Xinrui Wang, Nanjing University

July 14, 2025

Quantum Dot DBR Lasers Monolithically Integrated on Silicon Photonics by In-Pocket Heteroepitaxy

By Rosalyn Koscica, University of California

July 11, 2025

AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design

By Zichao Ling, Beijing University of Posts and Telecommunications

July 3, 2025