Optimizing Data Movement in SoCs and Advanced Packages
Andy Nightingale from Arteris talks about the demand for low-latency on-chip communication in increasingly complex devices, which can include chiplets, multiple networks on chip (NoCs), and the need for managing all of this with less power and using a simpler setup.
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Videos
- Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures
- Analyzing Packet Data Flow in Chiplet Based SoCs
- GENIOEVO™ – Architectural Exploration and Connectivity Management in Advanced Packaging
- Inside the AI Bottleneck: Data Movement, Chiplets, and System Scaling
Latest Videos
- Cadence & Samsung: Chiplet Ecosystem Innovation for Edge AI | CadenceLive 2026
- How to accelerate innovation in IC technology with chiplets and 3D ICs
- Automated Multiphysics for 3D IC Success
- Tying Together Chiplets using Network-on-Chip
- Inside the AI Bottleneck: Data Movement, Chiplets, and System Scaling