Cost Analysis of Chiplet Packaging Methods

By Amy Lujan, Sansys Solutions

Packaging consumes more of the chip cost as manufacturers move to smaller node dimensions. One issue with moving from monolithic designs to chiplets is the increased cost of packages due to the need to bond chiplets and provide interconnect among them. An available recent model covers three current types of packaging that support chiplets: substrate packaging (flip-chip), redistribution layer (RDL) packaging (fan-out), and silicon-interposer packaging (2.5D). The model has been validated using sample designs. It not only computes the cost of specific designs, but also allows designers to evaluate tradeoffs. For example, they could see the effects of changes such as adjusting the substrate structure, adding an RDL, or increasing the interposer’s size. The model thus offers designers a look into the costs of different packaging technologies and options. Future extensions will cover 3D packages and hybrid bonding.