GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package
By Galib Ibne Haidar, Kimia Zamiri Azar, Hadi M Kamali, Mark Tehranipoor, Farimah Farahmandi
University of Florida, USA
A heterogeneous integrated system in package (SIP) system integrates chiplets outsourced from different vendors into the same substrate for better performance. However, during post-integration testing, the sensitive testing data designated for a specific chiplet can be blocked, tampered or sniffed by other malicious chiplets. This paper proposes GATE-SiP which is an authenticated partial encryption protocol to enable secure testing. Within GATE-SiP, the sensitive testing pattern will only be sent to the authenticated chiplet. In addition, partial encryption of the sensitive data prevents data sniff threats without causing significant penalties on timing overhead. Extensive simulation results show the GATE-SiP protocol only brings 6.74% and 14.31% on area and timing overhead, respectively.
To read the full article, click here
Related Chiplet
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
Related Technical Papers
- Reliability challenges in 3D IC semiconductor design
- Why package lithography matters in heterogeneous chiplet integration
- What’s Next for Multi-Die Systems in 2024?
- The Next Frontier in Semiconductor Innovation: Chiplets and the Rise of 3D-ICs
Latest Technical Papers
- FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates
- ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification
- ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC
- Advanced Chiplet Placement and Routing Optimization considering Signal Integrity
- Building Advanced 3D Devices with DBI®