Heterogeneous 2.5/3D Chip Design Requires Integrated Tools
The latest high performance chips often employ 2.5D and 3D chip technologies like chiplets to deliver their functionality within the required cost, power and performance requirements. Companies are moving from system-based optimization to design-based optimization as system design and packaging become more complex.
Kevin Rinebold, Account Technology Manager for Advanced Packaging at Siemens EDA talked about the changes in the industry and Siemens’ tools that address this space and the Siemens “cockpit.”
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Videos
- Data Routing In Heterogeneous Chip Designs
- Revolutionizing System Design: Impact of Chiplets and Heterogeneous Integration on AI Server
- Tools for Testing Chiplet-based Designs
- Chiplets – The next generation chip design trend beyond Moore’s Law
Latest Videos
- From ASIC Startups to Chiplets: Decades of Semiconductor Leadership and Innovation | Kash Johal
- Chiplet Quilting for the Age of Inference
- DreamBig Semiconductor's Journey From Seed to Series B Funding for Their Multi-Die AI Chiplet
- Scaling a chiplet-based quantum processor toward fault-tolerance
- Splitting the Die A Modular Approach to Chiplet Design and Verification