A sneak peek at chiplet standards
By Majeed Ahmad, EDN (September 4, 2023)
The scaling of system-on-chip (SoC) architectures is hitting the wall, paving the way for die-to-die interconnect in heterogenous single-package systems commonly known as chiplets. But while these chiplet-optimized interconnect technologies are gaining significant traction, they are still in their infancy.
That makes chiplet interconnect standards crucial for the new multi-die semiconductors era. Below is a brief outline of three standards that are considered critical in the present evolution of chiplets. These standards will likely play a vital role in creating an open chiplet ecosystem.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- InPsytech showcases 3nm UCIe 3.0 technology at OCP 2025, Accelerating Innovation in Chiplet Ecosystem
- Eliyan Showcases Next-Generation Chiplet Interconnect and Memory Innovations at OCP Global Summit 2025
- Alphawave Semi Showcases Advances in PCIe Over Optics and Chiplet Integration at SC25
- Tenstorrent Announces Open Chiplet Atlas™ Ecosystem to Accelerate and Standardize an Open Chiplet Ecosystem
Latest News
- Qualcomm Completes Acquisition of Alphawave Semi
- Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology
- Avnet ASIC and Bar-Ilan University Launch Innovation Center for Next Generation Chiplets
- SEMIFIVE Strengthens AI ASIC Market Position Through IPO “Targeting Global Markets with Advanced-nodes, Large-Die Designs, and 3D-IC Technologies”
- FormFactor Expands Silicon Photonics Test Capabilities With Acquisition of Keystone Photonics